The fabrication of integrated circuits devices is well known. They are manufactured by fabricating a plurality of active devices, such as field effect transistors (FET) and passive devices on and in a semiconductor wafer substrate, such as silicon. The transistors and devices are connected by conductive material, such as metal or polysilicon, in the form or conductive patterns. Normally, the metal is either aluminum including aluminum alloys or copper. A passivating layer is applied over the last or final conductive layer of the wafer for reliability purposes.
To achieve higher levels of integration and greater density of devices on the wafer, the present trend is to fabricate the interconnecting pattern with finer conductive lines and more layers and thereby make the upper surface of the wafer more complex. This complexity creates of the requirement of knowing whether the upper surface of the wafer is completely covered with the passivating material. Without such complete coverage, any uncoated integrated circuits would become unreliable.
Determining complete coverage of the wafer with the passivating material by measuring its thickness is difficult. In addition, the final wiring structure is deposited thick and substractively etched, adding to the difficulty of thickness measurement of the passivating material. Thus, there is a need for an accurate method to verify that the thickness of the passivating material is sufficient to completely cover the integrated circuits on the wafer. One solution would be to coat the wafer with an excess of the passivating material to more than completely cover the wafer. However, the passivating material is expensive and this solution would also reduce patterning accuracy of said passivation layer. Accordingly, an accurate method is needed for determining the complete coverage of the integrated circuits on the wafer without any wastage of the expensive passivating material.